`include "vmm_ral_host_itf.sv"
module apb2hostif
(
    input                                 pclk,
    input                                 presetn,
    input   [`VMM_RAL_ADDR_WIDTH     -1:0]paddr,
    input                                 psel,
    input                                 penable,
    input                                 pwrite,
    input   [`VMM_RAL_DATA_WIDTH     -1:0]pwdata,
    input   [(`VMM_RAL_DATA_WIDTH/8) -1:0]pstrb,   // realize part write of data & indicate that part of data in a transmission is valid.
    output                                pready,  // indicate the completion of APB transmission.
    output  [`VMM_RAL_DATA_WIDTH     -1:0]prdata,
    output                                pslverr, // indicate the error status if the slave
    vmm_ral_host_itf.master               mst
);

assign mst.sel  = {`VMM_RAL_ADDR_BYTES{psel && penable}};
assign mst.wen  = pwrite;
assign mst.wdat = pwdata;
assign mst.adr  = paddr;

assign pready   = 1'b1;
assign prdata   = mst.rdat;
assign pslverr  = 1'b0;

wire   pack     = mst.ack;

endmodule
